T8207 Datasheet, PDF (43/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
9 UTOPIA Interface (continued)
9.1 Incoming UTOPIA Cell Interface
9.1.1 Incoming PHY Mode (Cells Received by T8207)
In PHY mode, only one enable (u_rxenb*[0]) signal and one cell available (u_rxclav[0]) signal are used. The
u_rxenb*[0] signal is an input connected to the ATM layer’s TxEnb* signal, and the u_rxclav[0] signal is an output
connected to the ATM layer’s TxClav signal. As a PHY device, the T8207 uses only the LUT 0 configuration/status
register (address 0320h) and LUT 0 configuration 1 registers (addresses 0704h—0706h). For UTOPIA level 2
functionality, the PHY address is programmed in the addr_match bits of the UTOPIA configuration register
(address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be pro-
grammed to any value mentioned in the register except “000.” As specified in the UTOPIA level 2 specification,
during the polling process, the T8207 drives the u_rxclav[0] signal during the clock cycle following the cycle in
which its address appears on the u_rxaddr pins. The u_rxclav[0] pin goes high impedance when not selected to
support MPHY operation. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en
bits must be programmed to “000,” the u_rxaddr pins must be grounded, and the addr_match bits cleared.
When the T8207 device is in PHY mode, if bit 5 (dont_inhibit_rxphy_clav) of register 0112h is cleared to ‘0,’ the
rx_clav signal is deasserted if the RX UTOPIA FIFO is considered full. If this bit is set to ‘1,’ the T8207 keeps the
rx_clav signal always asserted high indicating the capability to accept cells even if the RX UTOPIA FIFO could
overrun, or is actually overrun.
9.1.2 Incoming ATM Mode (Cells Received by T8207)
In ATM mode, the T8207 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If
the connection is to devices that meet only UTOPIA level 1 specifications, the T8207 may access up to four of
these PHY devices using the four enable (u_rxenb*[3:0]) and cell available (u_rxclav[3:0]) signals. Connection to
more than one PHY device is possible only if the PHY’s data, start of cell, and parity outputs go high impedance
when the device is not enabled. Polling of the cell available signals usually occurs while the current cell is received.
If the T8207 connects to PHY devices meeting level 2 UTOPIA specifications, one RxCLAV/RxENB pair supports
up to 16 PHY ports. For 32 PHY ports, two RxCLAV/RxENB pairs support two groups of 16 PHY ports for a total of
32 PHY ports. In ATM MPHY mode, the u_rxdata[7:0], u_rxaddr[4:0], u_rxsoc, and u_rxprty signals are connected
to each PHY port. In addition, the T8207 generates the address (u_rxaddr[4:0]) signals, permitting selection and
arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four,
giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.)
Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell
available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used
when the T8207 connects to multiple level 2 PHY devices.
Whether the T8207 is connected to several level 1 or level 2 PHY devices, a round-robin algorithm is implemented
that ensures that all PHY devices are serviced (accessed) in a timely manner. In addition, the number of clock
cycles wasted for bus arbitration is minimized because polling is performed during cell transfer.
In ATM mode, all unused u_rxclav inputs require connection to ground.
Note: The u_rxenb outputs are high impedance during powerup and reset. An attached PHY may interpret this
high-impedance state as an enable; however, the T8207 is not ready to properly handle input data during
this time. Attach pull-up resistors to these outputs if a problem is anticipated.
When the T8207 is in ATM mode, if bit 6 (inhibit_rxuto_fifo_overrun) of register 0112h is set to ‘1,’ the T8207 pre-
vents the RX UTOPIA FIFO from overflowing by deasserting its rx_enb* signal even though the rx_clav signal is
high when polled, if the RX UTOPIA FIFO is considered full. If this bit is cleared to ‘0,’ the rx_enb* signal is not
deasserted even if the RX UTOPIA FIFO is considered full.
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