T8207 Datasheet, PDF (63/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
10 Cell Bus Interface (continued)
10.7 Cell Bus Write and Read Clocks
The read and write clocks (cb_wc* and cb_rc* pins) are supplied from an external source. The write clock should
be delayed 1.5 ns to 4 ns relative to the read clock to ensure sufficient data hold time. The position of the clock
source relative to the cell bus devices on the card or on connecting cards determines the actual delay that should
be used. When the clock source is centrally located among the cell bus devices, a longer delay may be used.
When the clock source is at either end of the cell bus devices, a shorter delay is needed. Also, a higher clock fre-
quency requires a shorter delay.
Agere Systems Inc.
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