T8207 Datasheet, PDF (95/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
14 Registers (continued)
Table 55. Main Interrupt Enable 1 (MIE1) (0104h)
Name
Bit Pos. Type Reset
Description
cb_wc_miss_ie
0
RW 0 Cell Bus Write Clock Missing Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
cb_rc_miss_ie
1
RW 0 Cell Bus Read Clock Missing Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
cb_fs_miss_ie
2
RW 0 Cell Bus Frame Synchronization Signal Missing Interrupt
Enable. An interrupt is generated if this bit and the corresponding
status bit are set. The interrupt is generated until this bit or the cor-
responding status bit is reset.
BIP8_err_ie
3
RW 0 Bit Interleave Parity Error Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is reset.
ctrl_cell_ack_ie
4
RW 0 Control Cell Acknowledged Interrupt Enable. An interrupt is gen-
erated if this bit and the corresponding status bit are set. The inter-
rupt is generated until this bit or the corresponding status bit is reset.
ctrl_cell_nack_ie
5
RW 0 Control Cell Not Acknowledged Interrupt Enable. An interrupt is
generated if this bit and the corresponding status bit are set. The
interrupt is generated until this bit or the corresponding status bit is
reset.
cb_grnt_to_ie
6
RW 0 Cell Bus Grant Time-Out Interrupt Enable. An interrupt is gener-
ated if this bit and the corresponding status bit are set. The interrupt
is generated until this bit or the corresponding status bit is reset.
ctrl_cell_sent_ie
7
RW 0 Control Cell Sent Interrupt Enable. An interrupt is generated if this
bit and the corresponding status bit are set. The interrupt is gener-
ated until this bit or the corresponding status bit is reset.
ctrl_cell_av_ie
8
RW 0 Control Cell Available Interrupt Enable. An interrupt is generated
if this bit and the corresponding status bit are set. The interrupt is
generated until this bit or the corresponding status bit is reset.
cb_rh_crc_err_ie
9
RW 0 Cell Bus Routing Header CRC Error Interrupt Enable. An inter-
rupt is generated if this bit and the corresponding status bit are set.
The interrupt is generated until this bit or the corresponding status
bit is reset.
rx_prty_err_ie
10 RW 0 Receive Parity Error Interrupt Enable. An interrupt is generated if
this bit and the corresponding status bit are set. The interrupt is gen-
erated until this bit or the corresponding status bit is reset.
soc_err_ie
11 RW 0 Start of Cell Error Interrupt Enable. An interrupt is generated if
this bit and the corresponding status bit are set. The interrupt is gen-
erated until this bit or the corresponding status bit is reset.
Reserved
15:12 RO 0 Reserved.
Agere Systems Inc.
95