T8207 Datasheet, PDF (46/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
9 UTOPIA Interface (continued)
If the T8207_sel bit is set and 16 or less ports are used, then each port uses four queues with priorities from 0 to 3,
where 0 is the highest priority and 3 is the lowest priority. The lowest-numbered queue in the group of four is
assigned priority 0, and the highest-numbered queue in the group is assigned priority 3. For 32 PHY ports, any of
the four queues in each group may be assigned to either the even- or odd-numbered port. An example, which will
be called normal 32-port mode, assigns queues with priorities of 0 and 2 to the even-numbered ports and queues
with priorities of 1 and 3 to the odd-numbered ports. See the port_rte[63:48], port_rte[47:32], port_rte[31:16] and
port_rte[15:0] bits in the TX PHY FIFO routing 3, 2, 0, and 1 (addresses 0178h, 017Ah, 017Ch, and 017Eh) regis-
ters, respectively. Figure 11 illustrates the selection of ports when 32 are used.
If the T8207_sel bit in the main configuration 2 register (Table ) is cleared, the device cannot be configured to
access 32 PHY ports. Only 16 PHYs and 32 queues are available. For 16 PHY ports, any of the four queues in
each group may be assigned to either the even- or odd-numbered port. An example, which will be called normal
16-port mode, assigns queues with priorities of 0 and 2 to the even-numbered ports and queues with priorities of 1
and 3 to the odd-numbered ports.
PRIORITY
CELL BUS
128
CELL
FIFO
QUEUE 0
QUEUE 1
QUEUE 2
QUEUE 3
QUEUE 60
QUEUE 61
QUEUE 62
QUEUE 63
P0
P1
HP
P2
P3
P4
P5
P6
LP
P7
P8
P9
DEMULTIPLEXER CONTROLLED BY
P10
PORT_RTE[63:48], PORT_RTE[47:32],
PORT_RTE[31:16], PORT_RTE[15:0]
IN TX PHY FIFO ROUTING
3, 2, 0, AND 1 REGISTERS
(ADDRESSES 0178h, 017Ah, 017Ch, 017Eh)
P30
P31
Figure 11. Queue Priority Multiplexing
TX UTOPIA PORT
5-7784.b F
The TX UTOPIA cell buffer is kept full by cells transferred to it from the SDRAM. Each port has equal priority for
transmitting onto the UTOPIA bus. The cell transmitted by any one port is determined by the priority of its queues
with cells waiting to be transmitted. In addition, the number of clock cycles wasted for bus arbitration is minimized
because polling is performed during cell transfer.
Cells arriving from the cell bus have their header error check (HEC) bytes removed. Therefore, the T8207 calcu-
lates the HEC and inserts it into each cell before transmitting it onto the UTOPIA bus. See Figure 12.
9.3 Counters
For each port selected in MPHY mode, two 16-bit registers (in_cnt_phyX[31:16] and in_cnt_phyX[15:0] in Table
102) are used as a 32-bit free-running incoming cell counter. Each port’s counter counts valid and misrouted
incoming cells. Incoming cells are not counted if they encounter an ignore (I) bit in their translation records that is
‘1’ or if their VPI and/or VCI are out of range. The counter for port 0 is found at addresses 0700h and 0702h. See
Table 102 in Section 14.3.2.3, RX UTOPIA Monitoring, for the addresses of other ports' incoming cell counters.
Also, for each port selected in MPHY mode, two 16-bit registers (out_cnt_phyX[31:16] and out_cnt_phyX[15:0] in
Table 101) are used as a 32-bit free-running outgoing cell counter. Each port's counter counts all outgoing cells to
the UTOPIA bus. The counter for port 0 is found at addresses 0600h and 0602h. See Table 101 in Section
14.3.2.2, TX UTOPIA Monitoring, for the addresses of other ports' outgoing cell counters.
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