T8207 Datasheet, PDF (84/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 28. Interrupt Service Request (ISREQ) (29h)
Name
Bit Pos. Type
Reserved
0
RO
int_serv_mainreg
1
RO
int_serv_sdramreg 2
RO
int_serv_utopiareg 3
RO
Reserved
4
RO
ctrl_cell_sent_sr
5
RO
ctrl_cell_av_sr
6
RO
Reserved
7
RO
Reset
Description
0 Reserved.
0 Interrupt Service Request for Main Registers. When this bit is
‘1,’ an interrupt in the main register group of the extended mem-
ory registers needs servicing. The control cell sent and control
cell available status bits do not affect this bit. Only enabled inter-
rupts will cause this bit to become set.
0 Interrupt Service Request for SDRAM Registers. When this bit
is ‘1,’ an interrupt in the SDRAM register group of the extended
memory registers needs servicing. Only enabled interrupts will
cause this bit to become set.
0 Interrupt Service Request for UTOPIA Registers. When this bit
is ‘1,’ an interrupt in the UTOPIA register group of the extended
memory registers needs servicing. Only enabled interrupts will
cause this bit to become set.
0 Reserved.
0 Control Cell Sent Interrupt Service Request. When this bit is
‘1,’ the control cell sent interrupt in the main interrupt status 1
register needs servicing. The corresponding interrupt does not
need to be enabled for this bit to become set.
0 Control Cell Available Interrupt Service Request. When this
bit is ‘1,’ the control cell available interrupt in the main interrupt
status 1 register needs servicing. The corresponding interrupt
does not need to be enabled for this bit to become set.
0 Reserved.
Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah)
Name
lf[3:0]
Reserved
bypb
pllen
Bit Pos.
3:0
5:4
6
7
Type
RW
RO
RW
RW
Reset
Description
0 Loop Filter. See Section 5, PLL Configuration, for information on
these bits.
0 Reserved.
0 Bypass PLL. If this bit is ‘0,’ the PLL is bypassed. If ‘1,’ the output
of the PLL supplies mclk.
0 PLL Enable. If this bit is ‘1,’ the PLL is enabled. If ‘0,’ the PLL is
disabled.
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