T8207 Datasheet, PDF (94/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
Table 54. Main Interrupt Status 1 (MIS1) (0102h)
Name
Bit Pos.
cb_wc_miss
0
cb_rc_miss
1
cb_fs_miss
2
BIP8_err
3
ctrl_cell_ack
4
ctrl_cell_nack
5
cb_grnt_to
6
ctrl_cell_sent
7
ctrl_cell_av
8
cb_rh_crc_err 9
rx_prty_err
10
soc_err
11
Reserved 15:12
Type
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
RO
Reset
Description
0 Cell Bus Write Clock Missing. This bit is set when the cell bus write
clock is inactive for 32 mclk cycles. An interrupt is generated if the cor-
responding enable bit is set.
0 Cell Bus Read Clock Missing. This bit is set when the cell bus read
clock is inactive for 32 mclk cycles. An interrupt is generated if the cor-
responding enable bit is set.
0 Cell Bus Frame Synchronization Signal Missing. This bit is set
when the cell bus frame sync is not asserted every 16 read clock
cycles in 16-user mode, or every 32 read clock cycles in 32-user
mode. It is also set when cell bus write clock is not present because
the frame synchronization signal is clocked onto the cell bus by the
write clock. An interrupt is generated if the corresponding enable bit is
set.
0 Bit Interleave Parity Error. This bit is set when an error is detected in
the BIP-8 field of the last cell bus frame cycle. An interrupt is gener-
ated if the corresponding enable bit is set.
0 Control Cell Acknowledged. This bit is set when a control cell is
sent on the cell bus and an acknowledge is received. This bit is not
set for broadcast or multicast cells. An interrupt is generated if the cor-
responding enable bit is set.
0 Control Cell Not Acknowledged. This bit is set when a control cell is
sent on the cell bus and an acknowledge is not received. This bit is
not set for broadcast or multicast cells. An interrupt is generated if the
corresponding enable bit is set.
0 Cell Bus Grant Time-Out. This bit is set when a cell bus request has
not been granted within the time programmed in the cb_req_to bits.
An interrupt is generated if the corresponding enable bit is set.
0 Control Cell Sent. This bit is set when a control cell is sent onto the
cell bus. An interrupt is generated if the corresponding enable bit is
set.
0 Control Cell Available. This bit is set when a control cell is waiting to
be read by the microprocessor. An interrupt is generated if the corre-
sponding enable bit is set.
0 Cell Bus Routing Header CRC Error. This bit is set when an error is
detected in the CRC field of the cell bus routing header. An interrupt is
generated if the corresponding enable bit is set.
0 Receive Parity Error. This bit is set when the odd parity calculated
over the data received on the RX UTOPIA port does not match the
u_rxprty signal. An interrupt is generated if the corresponding enable
bit is set. When a receive parity error occurs, the cell is still counted as
received and is translated and routed.
0 Start of Cell Error. This bit is set when a SOC framing error is
detected on the RX UTOPIA port. An interrupt is generated if the cor-
responding enable bit is set. When a start of cell error occurs, the
received cells are dropped.
0 Reserved.
Note: Immediately following device setup, write FFFFh to this register to clear erroneously set bits.
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