T8207 Datasheet, PDF (156/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
19 Timing Requirements (continued)
19.5 SDRAM Interface Timing
t1
SD_CLK*
SD_RAS*
SD_CAS*
SD_WE*
SD_BS[1:0]
SD_A[11:0]
SD_D[15:0]
(SOURCED BY T8207)
SD_D[15:0]
(SAMPLED BY T8207)
Note: 15 pF load on outputs.
Figure 30. SDRAM Interface Timing
Table 148. SDRAM Interface Timing
Symbol
Parameter
Min
t1
sd_clk Rising to Outputs Valid
—
t2
sd_clk Rising to Outputs Invalid
1.5
t3
sd_d[15:0] Input Setup to sd_clk Rising Edge
3
t4
sd_d[15:0] Input Hold from sd_clk Rising Edge
0
Advance Data Sheet
September 2001
t2
t3
t4
5-7798BF
Typ
Max Unit
—
7
ns
—
—
ns
—
—
ns
—
—
ns
156
Agere Systems Inc.