T8207 Datasheet, PDF (86/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
14 Registers (continued)
14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h
Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h)
Name
Reserved
ext_a[8:6]
Bit Pos.
4:0
7:5
Type
RO
RW
Reset
Description
0 Reserved.
0 Extended Access Address [8:6]. This extended access register
points to words.
Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h)
Name Bit Pos. Type Reset
Description
ext_a[16:9] 7:0 RW 0 Extended Access Address [16:9]. This extended access register
points to words.
Table 35. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h)
Name Bit Pos. Type Reset
Description
ext_a[24:17] 7:0 RW 0 Extended Access Address [24:17]. This extended access register
points to words.
Table 36. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h)
Name
ext_a[25]
Reserved
Bit Pos.
0
7:1
Type
RW
RO
Reset
Description
0 Extended Access Address [25]. This extended access register
points to words.
0 Reserved.
Table 37. Extended Memory Access (Little Endian) (EMA_LE) (34h)
Name
ext_a[5:1]
ext_we[1:0]
ext_strt_acc
Bit Pos.
4:0
6:5
7
Type
RW
RW
RW
Reset
Description
0 Extended Access Address [5:1]. This extended access register
points to words. ext_a[0] is hardwired to ‘0.’
0 Extended Access Write Enable. These bits are active-high write
enables for word accesses. If both bits are low, a read is performed. If
ext_we[1] is high, the contents of ext_d[15:8] are written, and if
ext_we[0] is high, the contents of ext_d[7:0] are written. If both bits are
high, both data bytes are written.
0 Start Access to Extended Memory. Write a ‘1’ to this bit to start the
access to the extended memory registers. This bit is automatically
cleared when the access is complete.
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