T8207 Datasheet, PDF (55/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
10 Cell Bus Interface (continued)
The cell bus may be configured for 16-user or 32-user mode using the cb_usr_mode bit in the cell bus configura-
tion/status register (address 0130h). In 16-user mode, all 16 devices assert their transmission requests during the
first cycle of each frame, and the transmission grant for the next frame is given during the last cycle of the frame. In
32-user mode, the frame synchronization signal is asserted every two cell bus frames. The two frames are termed
the odd and even frames. The frame synchronization signal marks the beginning of the even frame, and the odd
frame starts 16 clock cycles later. During the request cycle of the even frame, devices zero through 15 assert their
transmission requests, and during the request cycle of the odd frame, devices 16 through 31 assert theirs.
Requests received from odd and even frames are serviced as a group, and grants are given in the order that the
requests are received with the highest priority serviced first with the same priority requests serviced using a round-
robin algorithm. Transmission grants for the next frame are always given at the end of the current frame.
Cells to be transmitted onto the cell bus come from three sources internal to the T8207. Data cells from the
UTOPIA bus are placed in the RX PHY FIFO to await transmission onto the cell bus. Control cells from the micro-
processor wait in the control cell TX FIFO, and loopback cells from the cell bus wait in the loopback FIFO. Cells
from these three FIFOs are priority multiplexed onto the cell bus output FIFO to be transmitted onto the cell bus.
Optional high priority can be established for data cells or control cells sent to the cell bus. If bit 9 in register 0130h
is cleared to ‘0’ then cells from the RX PHY FIFO have the highest priority, cells from the control cell TX FIFO have
next highest, and finally, cells from the loopback FIFO have the lowest. If bit 9 in register 0130h is set to ‘1,’ then
cells from the control cell TX FIFO have the highest priority, cells from the RX PHY FIFO have the next highest pri-
ority, and finally, cells from the loopback FIFO have the lowest priority. This bit on default is ‘0.’
Incoming cells may be broadcast, multicast, or single address types. The T8207 receiving device accepts single
address cells with an address field in the cell bus routing header that matches the device’s unit address. In addi-
tion, the device accepts all broadcast cells and certain multicast cells that it is configured to accept. (See Section
10.3.4, Multicast Routing (continued).) Before a cell is accepted, a check is done on the previous grant to verify
whether it is a valid grant or not. The receiving device verifies the cell bus routing header cyclic redundancy check
(CRC-4) value in the least significant 4 bits of the cell bus routing header. It also verifies the bit interleave parity
(BIP-8) value from bits 24 to 31 of the last cell bus frame cycle. If either is corrupt, the cell is discarded. If kept, cells
are routed to the loopback FIFO, control FIFO, or TX PHY FIFO, based on the information in its cell bus routing
header. See Section 10.3, Cell Bus Routing Headers.
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