T8207 Datasheet, PDF (146/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
19 Timing Requirements (continued)
19.1 Microprocessor Interface Timing
For access time information, see Section 6.3.2, CelXpres T8207 Access Performance.
t1
WRITE_ACCESS_ACTIVE¹
t2
t3
t7
A[7:0]
D[7:0]
RDY_DTACK*²
t4
t5
t6
1. write_access_active is the logical OR function of sel* and wr*_ds*.
2. Load is 15 pF.
Note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal.
5-7787bF
Figure 21. Nonmultiplexed Intel Mode Write Access Timing
t1
READ_ACCESS_ACTIVE¹
t2
t3
t9
A[7:0]
D[7:0]
RDY_DTACK*²
t4
t8
t7
t6
t5
1. read_access_active is the logical OR function of sel* and rd*_wr*.
2. Load is 15 pF.
Note: sel* and rd*_wr* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signals.
5-7788bF
Figure 22. Nonmultiplexed Intel Mode Read Access Timing
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