T8207 Datasheet, PDF (13/158 Pages) Agere Systems – ATM Interconnect

Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
2 Pin Description
This section defines the CelXpres T8207 pins. All TTL compatible inputs or I/O are 5 V tolerant. No GTL+ inputs or
I/O are 5 V tolerant.
Table 1. UTOPIA Pins
Symbol
u_rxaddr[4:0]
u_rxdata[7:0]
u_rxclk
u_rxsoc
u_rxclav[0]
u_rxclav[3:1]
u_rxenb*[0]
u_rxenb*[3:1]
u_rxprty
u_txaddr[4:0]
u_txdata[7:0]
u_txclk
u_txsoc
u_txclav[0]
u_txclav[3:1]
u_txenb*[0]
u_txenb*[3:1]
u_txprty
u_shr_o
u_shr_i
Ball
R2, P3, R1, P2,
P1
V2, U3, T4, V1,
U2, T3, U1, T2
T1
P4
L4
M3, M2, M1
M4
N3, N2, N1
R3
P17, R19, R20,
P18, P19
W20, V19, U19,
U18, T17, V20,
U20, T18
R18
T20
M20
M17, M18, M19
N20
P20, N18, N19
T19
V16
W17
Reset
Value
Z
—
Z
—
Z
—
Z
Z
—
Z
Z
Z
Z
Z
—
Z
Z
Z
1
—
Type
Name/Description
I/O RX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O,
5 V tolerant.
I RX UTOPIA Data Lines. TTL compatible input, 5 V tolerant.
I/O RX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.
I RX UTOPIA Start of Cell (Active-High). TTL compatible input,
5 V tolerant.
I/O RX UTOPIA PHY 0 Cell Available (Active-High). Main RX cell
available in single PHY mode. 10 mA drive, TTL compatible I/O, 5 V
tolerant. This pin has an internal 50 kΩ pull-up resistor.
I RX UTOPIA Cell Available Lines (Active-High). TTL compatible
input, 5 V tolerant. These pins have an internal 50 kΩ pull-up resis-
tor.
I/O RX UTOPIA PHY 0 Enable (Active-Low). Main RX enable in sin-
gle PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.
I/O RX UTOPIA PHY Enable Lines (Active-Low). 10 mA drive, TTL
compatible I/O, 5 V tolerant.
I RX UTOPIA Odd Parity. TTL compatible input, 5 V tolerant. This
pin has an internal 50 kΩ pull-up resistor.
I/O TX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O.
5 V tolerant.
O TX UTOPIA Data Lines. 10 mA drive, TTL compatible output.
I/O TX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.
O TX UTOPIA Start of Cell (Active-High). 10 mA drive, TTL compat-
ible output.
I/O TX UTOPIA PHY 0 Cell Available (Active-High). Main TX cell
available in single PHY mode. 10 mA drive, TTL compatible I/O. 5 V
tolerant. This pin has an internal 50 kΩ pull-up resistor.
I TX UTOPIA Cell Available Lines (Active-High). TTL compatible
input, 5 V tolerant. These pins have an internal 50 kΩ pull-up resis-
tor.
I/O TX UTOPIA PHY 0 Enable (Active-Low). Main TX enable in single
PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.
O TX UTOPIA Enable Lines (Active-Low). 10 mA drive, TTL com-
patible output.
O TX UTOPIA Odd Parity. 10 mA drive, TTL compatible output.
O Shared UTOPIA Output. Used as grant if device is shared
UTOPIA master or as request if device is shared UTOPIA slave.
4 mA drive, TTL compatible output. This pin has an internal 50 kΩ
pull-up resistor.
I Shared UTOPIA Input. Used as request if device is shared
UTOPIA master or as grant if chip is shared UTOPIA slave. TTL
compatible input, 5 V tolerant. This pin has an internal 50 kΩ pull-
up resistor.
Agere Systems Inc.
13