T8207 Datasheet, PDF (154/158 Pages) Agere Systems – ATM Interconnect

CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
19 Timing Requirements (continued)
The term mclkp in Tables 143, 144, 145, and 146, represents the period of mclk in ns.
Table 143. External LUT Memory Read Timing (cyc_per_acc = 2)
Symbol
Parameter
Min
t1 tr_oe* Low to tr_d[7:0] Driven by SRAM Chip
0
t2 tr_a[17:0] & tr_cs*[1:0] Valid to tr_d[7:0] Valid
0
t3 tr_oe* High to tr_d[7:0] Invalid
0
t4 tr_oe* High to tr_d[7:0] 3-State
—
Typ
Max
Unit
— 2 x mclkp – 11 ns
— 2 x mclkp – 11 ns
—
—
ns
—
mclkp
ns
Table 144. External LUT Memory Read Timing (cyc_per_acc = 3)
Symbol
Parameter
Min
t1 tr_oe* Low to tr_d[7:0] Driven by SRAM Chip
0
t2 tr_a[17:0] & tr_cs*[1:0] Valid to tr_d[7:0] Valid
0
t3 tr_oe* High to tr_d[7:0] Invalid
0
t4 tr_oe* High to tr_d[7:0] 3-State
—
Typ
Max
Unit
— 3 x mclkp – 11 ns
— 3 x mclkp – 11 ns
—
—
ns
—
mclkp
ns
Table 145. External LUT Memory Write Timing (cyc_per_acc = 2)
Symbol
Parameter
t1 tr_oe* High to tr_d[7:0] Driven
t2 tr_a[17:0] Setup to tr_we* Falling Edge
t3 tr_we* Low Pulse Width
t4 tr_d[7:0] Setup to tr_we* Rising Edge
t5 tr_d[7:0] Hold from tr_we* Rising Edge
t6 tr_a[17:0] Hold from tr_we* Rising Edge
t7 tr_d[7:0] 3-State to tr_oe* Low
Min
Typ
Max
Unit
mclkp – 4
—
—
ns
2
—
—
ns
mclkp – 1
—
—
ns
mclkp
—
—
ns
2
—
—
ns
2
—
—
ns
0
—
—
ns
Table 146. External LUT Memory Write Timing (cyc_per_acc = 3)
Symbol
Parameter
Min
Typ
Max
Unit
t1 tr_oe* High to tr_d[7:0] Driven
mclkp – 4
—
—
ns
t2 tr_a[17:0] Setup to tr_we* Falling Edge
2
—
—
ns
t3 tr_we* Low Pulse Width
2 x mclkp – 1 —
—
ns
t4 tr_d[7:0] Setup to tr_we* Rising Edge
2 x mclkp
—
—
ns
t5 tr_d[7:0] Hold from tr_we* Rising Edge
2
—
—
ns
t6 tr_a[17:0] Hold from tr_we* Rising Edge
2
—
—
ns
t7 tr_d[7:0] 3-State to tr_oe* Low
0
—
—
ns
154
Agere Systems Inc.