Z8FMC16100 Datasheet, PDF (86/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
64
Table 39. Watch-Dog Timer Approximate Time-Out Delays
WDT Reload
Value (Hex)
0400
FFFF
WDT Reload
Value
(Decimal)
1024
65,536
Approximate Time-Out Delay
(with 10 KHz Typical WDT Oscillator Frequency)
Typical Description
102ms Reset default value time-out delay.
6.55s Maximum time-out delay.
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 0000h unless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the down-
counter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload
registers. Counting resumes following the reload operation.
When the Z8FMC16100 Series Flash MCU is operating in DEBUG Mode (through the
On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent spurious
Watch-Dog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 0000h. A time-out of the
Watch-Dog Timer generates either a system exception or a Reset. The WDT_RES Option
Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits
chapter for information regarding programming of the WDT_RES Option Bit.
WDT System Exception in Normal Operation
If configured to generate a system exception when a time-out occurs, the Watch-Dog
Timer issues an exception request to the interrupt controller. The eZ8 CPU responds to the
request by fetching the System Exception vector and executing code from the vector
address. After time-out and system exception generation, the Watch-Dog Timer is
reloaded automatically and continues counting.
WDT System Exception in Stop Mode
If configured to generate a system exception when a time-out occurs and the
Z8FMC16100 Series Flash MCU is in STOP mode, the Watch-Dog Timer automatically
initiates a Stop-Mode Recovery and generates a system exception request. Both the WDT
status bit and the STOP bit in the Reset Status and Control Register section on page 29 are
set to 1 following WDT time-out in STOP mode. Refer to the Reset and Stop-Mode
Recovery chapter on page 23 for more information.
Watch-Dog Timer
PRELIMINARY
PS024604-1005