Z8FMC16100 Datasheet, PDF (197/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
175
7. The I²C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL.
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit, and clears the ACK bit in the I²C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I²C controller flushes the Transmit Data Register,
sends a STOP condition on the bus, and clears the STOP and NCKI bits. The transaction
is complete, and the following steps can be ignored.
8. The I²C controller shifts in the first byte of data from the I²C slave on the SDA signal.
9. The I²C controller asserts the receive interrupt.
10. The software responds by reading the I²C Data Register. If the next data byte is to be
the final byte, the software must set the NAK bit of the I²C Control Register.
11. The I²C controller sends a Not Acknowledge to the I²C slave if the next byte is the
final byte; otherwise, it sends an Acknowledge.
12. If there are more bytes to transfer, the I²C controller returns to Step 7.
13. A NAK interrupt (NCKI bit in I2CISTAT) is generated by the I²C controller.
14. The software responds by setting the STOP bit of the I²C Control Register.
15. A STOP condition is sent to the I²C slave.
Master Read Transaction with a 10-Bit Address
Figure 31 illustrates the read transaction format for a 10-bit addressed slave.
S Slave Address W=0 A Slave Address A S Slave Address R=1 A Data A Data A P
1st Byte
2nd Byte
1st Byte
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XX bits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I²C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I²C Control Register.
2. The software writes 11110b, followed by the two most-significant address bits and a
0 (write) to the I²C Data Register.
PS024604-1005
PRELIMINARY
Master Transactions