Z8FMC16100 Datasheet, PDF (205/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
183
d. Set IEN = 1, NAK = 0 in the I²C Control Register.
2. The master initiates a transfer, sending the first address byte. The SLAVE mode I²C
controller recognizes the start of a 10-bit address with a match to SLA[9:8] and
detects the R/W bit = 0 (a Write from the master to the slave). The I²C controller
acknowledges, indicating it is available to accept the transaction.
3. The master sends the second address byte. The SLAVE mode I²C controller compares
the second address byte with the value in SLA[7:0]. If there is a match, the SAM bit in
the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RD bit
is set = 0, indicating a write to the slave. If a match occurs, the I²C controller acknowl-
edges on the I²C bus, indicating it is available to accept the data.
4. The software responds to the slave address match interrupt by reading the I2CISTAT
Register, which clears the SAM bit. Because the RD bit = 0, no further action is
required.
5. The master sees the Acknowledge and sends a RESTART instruction, followed by the
first address byte with the R/W set to 1. The SLAVE mode I²C controller recognizes
the RESTART instruction followed by the first address byte with a match to
SLA[9:8], and detects the R/W = 1 (the master reads from the slave). The slave I²C
controller sets the SAM bit in the I2CISTAT Register, which causes the slave address
match interrupt. The RD bit is set = 1. The SLAVE mode I²C controller acknowledges
on the bus.
6. The software responds to the interrupt by reading the I2CISTAT Register, clearing the
SAM bit. The software loads the initial data byte into the I2CDATA Register and sets
the TXI bit in the I2CCTL Register.
7. The master starts the data transfer by asserting SCL Low. After the I²C controller has
data available to transmit, the SCL is released, and the master proceeds to shift the
first data byte.
8. After the first bit of the first data byte has been transferred, the I²C controller sets the
TDRE bit which asserts the transmit data interrupt.
9. The software responds to the transmit data interrupt by loading the next data byte into
the I2CDATA Register.
10. The I²C master shifts in the remainder of the data byte. The master transmits the
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I²C controller holds SCL Low until the
data register is written.
When a Not Acknowledge is received by the slave, the I²C controller sets the NCKI bit
in the I2CISTAT Register, causing the NAK interrupt to be generated.
PS024604-1005
PRELIMINARY
Slave Transactions