Z8FMC16100 Datasheet, PDF (195/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
173
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I²C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I²C Control Register.
2. The software asserts the TXI bit of the I²C Control Register to enable transmit inter-
rupts.
3. The I²C interrupt asserts because the I²C Data Register is empty.
4. The software responds to the TDRE interrupt by writing the first slave address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. The software asserts the START bit of the I²C Control Register.
6. The I²C controller sends a START condition to the I²C slave.
7. The I²C controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
asserts.
9. The software responds by writing the second byte of address into the contents of the
I²C Data Register.
10. The I²C controller shifts the remainder of the first byte of the address and the Write bit
out via the SDA signal.
11. The I²C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I²C controller sets the ACK bit in the I²C Status Register.
If the slave does not acknowledge the first address byte, the I²C controller sets the
NCKI bit in the I²C Status Register, sets the ACKV bit, and clears the ACK bit in the I²C
State Register. The software responds to the Not Acknowledge interrupt by setting the
STOP bit and clearing the TXI bit. The I²C controller flushes the second address byte
from the data register, sends a STOP condition on the bus, and clears the STOP and
NCKI bits. The transaction is complete, and the following steps can be ignored.
12. The I²C controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister (2nd address byte).
13. The I²C controller shifts the second address byte out via the SDA signal. After the
first bit has been sent, the transmit interrupt asserts.
14. The software responds by writing the data to be written out to the I²C Control Regis-
ter.
15. The I²C controller shifts out the remainder of the second byte of the slave address (or
ensuing data bytes, if looping) via the SDA signal.
PS024604-1005
PRELIMINARY
Master Transactions