Z8FMC16100 Datasheet, PDF (139/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
117
1. Check the LIN-UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was due to data available, read the data from the LIN-UART Receive
Data Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the multiprocessor mode bits MPMD[1:0].
3. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send Operation
The Clear To Send (CTS) pin, if enabled by the CTSE bit of the LIN-UART Control 0 Reg-
ister, performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before beginning any new character trans-
mission. To delay transmission of the next data character, an external receiver must deas-
sert CTS at least one system clock cycle before a new data transmission begins. For
multiple character transmissions, this operation is typically performed during the Stop Bit
transmission. If CTS deasserts in the middle of a character transmission, the current char-
acter is sent completely.
External Driver Enable
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is a programmable polarity signal that envelopes the entire transmitted data
frame including parity and Stop bits as illustrated in Figure 14. The Driver Enable signal
asserts when a byte is written to the LIN-UART Transmit Data Register. The Driver
Enable signal asserts at least one bit period and no greater than two bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the last Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Regis-
ter before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The DEPOL bit in the LIN-UART Control Register 1 sets the polarity
of the Driver Enable signal.
PS024604-1005
PRELIMINARY
Clear To Send Operation