Z8FMC16100 Datasheet, PDF (229/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
207
Table 109. Sample Hold Time (ADCST)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
ST
RESET
0
1
1
1
1
1
1
R/W
R/W
R/W
ADDR
F75H
Bit
Position
[7:6]
Value
(H)
0H
Description
Reserved - Must be 0.
[5:0]
SHT
0H - FH Sample Hold time in number of system clock periods to meet 1 µS minimum.
ADC Clock Prescale Register
The ADC Clock Prescale Register, shown in Table 110, is used to provide a divided sys-
tem clock to the ADC. When this register is programmed with 0h, the System Clock is
used for the ADC Clock.
BITS
FIELD
RESET
R/W
ADDR
Table 110. ADC Clock Prescale Register (ADCCP)
7
6
5
4
3
Reserved
DIV16
0
0
R/W
F76H
2
DIV8
0
1
DIV4
0
0
DIV2
0
Bit
Position
[0]
DIV2
Value
(H)
0
1
Description
DIV2
Clock is not divided
System Clock is divided by 2 for ADC Clock
PS024604-1005
PRELIMINARY
ADC Clock Prescale Register