Z8FMC16100 Datasheet, PDF (191/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
169
Start and Stop Conditions
The master generates the START and STOP conditions to start or end a transaction. To
start a transaction, the I²C controller generates a START condition by pulling the SDA sig-
nal Low while SCL is High. To complete a transaction, the I²C controller generates a
STOP condition by creating a Low-to-High transition of the SDA signal while the SCL
signal is High. These START and STOP events occur when the START and STOP bits in
the I²C Control Register are written by software to begin or end a transaction. Any byte
transfer currently under way, including the Acknowledge phase, finishes before the
START or STOP condition occurs.
Software Control of I²C Transactions
The I²C controller is configured via the I²C Control and I²C Mode registers. The
MODE[1:0] field of the I²C Mode Register allows the configuration of the I²C controller
for MASTER/SLAVE or SLAVE ONLY mode, and configures the slave for 7- or 10-bit
addressing recognition.
MASTER/SLAVE mode can be used for:
• MASTER ONLY operation in a single master/one or more slave I²C system
• MASTER/SLAVE in a multimaster/multislave I²C system
• SLAVE ONLY operation in an I²C system
In SLAVE ONLY mode, the START bit of the I²C Control Register is ignored (software
cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is
restricted, thereby preventing accidental operation in MASTER mode.
The software can control I²C transactions by enabling the I²C controller interrupt in the
interrupt controller or by polling the I²C Status Register.
To use interrupts, the I²C interrupt must be enabled in the interrupt controller and followed
by executing an EI instruction. The TXI bit in the I²C Control Register must be set to
enable transmit interrupts. An I²C interrupt service routine then checks the I²C Status
Register to determine the cause of the interrupt.
To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS, and NCKI inter-
rupt bits in the I²C Status Register should be polled. The TDRE bit asserts regardless of the
state of the TXI bit.
Master Transactions
The following sections describe master Read and Write transactions to both 7- and 10-bit
slaves.
PS024604-1005
PRELIMINARY
Start and Stop Conditions