Z8FMC16100 Datasheet, PDF (212/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
190
BITS
FIELD
RESET
R/W
ADDR
Table 98. I²C State Register (I2CSTATE) - Description when DIAG = 1
7
6
5
4
3
2
1
0
I2CSTATE_H
I2CSTATE_L
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
F55H
I2CSTATE_H—I²C State
This field defines the current state of the I²C Controller. It is the most significant nibble of
the internal state machine. Table 99 defines the states for this field.
I2CSTATE_L—Least significant nibble of the I²C state machine. This field defines the
substates for the states defined by I2CSTATE_H. Table 100 defines the values for this
field.
Table 99. I2CSTATE_H
State
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
State Name
Idle
Slave Start
Slave Bystander
Slave Wait
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Slave Transmit Data
Slave Receive Data
Slave Receive Addr1
Slave Receive Addr2
State Description
I²C bus is idle or I²C controller is disabled.
I²C controller has received a START condition.
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
Master completing STOP condition (SCL = 1, SDA = 1).
MASTER mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
9 substates, one for each data bit and one for the Acknowledge.
9 substates, one for each data bit and one for the Acknowledge.
Slave receiving first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
Slave Receiving second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
I2C Master/Slave Controller
PRELIMINARY
PS024604-1005