Z8FMC16100 Datasheet, PDF (189/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
167
I²C Interrupts
The I²C controller contains multiple interrupt sources that are combined into one interrupt
request signal to the interrupt controller. If the I²C controller is enabled, the source of the
interrupt is determined by which bits are set in the I2CISTAT Register. If the I²C control-
ler is disabled, the BRG controller can be used to generate general-purpose timer inter-
rupts.
Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.
Transmit Interrupts
Transmit interrupts (TDRE bit = 1 in I2CISTAT) occur under the following conditions, both
of which must be true.
• The transmit data register is empty and the TXI bit = 1 in the I²C Control Register
• The I²C controller is enabled, with one of the following:
– The first bit of a 10-bit address is shifted out
– The first bit of the final byte of an address is shifted out and the RD bit is deas-
serted
– The first bit of a data byte is shifted out
Writing to the I²C Data Register always clears the TRDE bit to 0.
Receive Interrupts
Receive interrupts (RDRF bit = 1 in I2CISTAT) occur when a byte of data has been
received by the I²C controller. The RDRF bit is cleared by reading from the I²C Data Reg-
ister. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I²C controller holds SCL Low during the final data bit of the next byte until
RDRF is cleared, to prevent receive overruns. A receive interrupt does not occur when a
slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE
Register, in which case Receive interrupts occur for all Receive address and data bytes in
SLAVE mode.
Slave Address Match Interrupts
Slave address match interrupts (SAM bit = 1 in I2CISTAT) occur when the I²C controller is
in SLAVE mode and an address is received that matches the unique slave address. The
General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the
GCE bit = 1 in the I2CMODE Register. The software checks the RD bit in the I2CISTAT
Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the RD bit. The General Call
PS024604-1005
PRELIMINARY
I²C Interrupts