Z8FMC16100 Datasheet, PDF (49/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
27
External Pin Reset
The input-only RESET pin has a Schmitt-triggered input, an internal pull-up, an analog
filter and a digital filter to reject noise. Once the RESET pin is asserted for at least 4 sys-
tem clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the Z8FMC16100 Series Flash MCU device continues
to be held in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state 16 system clock cycles following RESET pin deasser-
tion. If the RESET pin is released before the System Reset time-out, the RESET pin is
driven Low by the chip until the completion of the time-out as described in the next sec-
tion. In STOP mode the digital filter is bypassed because the System Clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
Reset Status and Control Register is set to 1.
External Reset Indicator
During System Reset, the RESET pin functions as an open drain (active Low) reset mode
indicator in addition to the input functionality. This reset output feature allows a
Z8FMC16100 Series Flash MCU device to reset other components to which it is con-
nected, even if the reset is caused by internal sources such as POR, VBO, or WDT events
and as an indication of when the reset sequence completes.
Once an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 6 has elapsed.
On-Chip Debugger Initiated Reset
A System Reset may be initiated via the On-Chip Debugger by setting RST bit of the
OCDCTL register. The On-Chip Debugger is not reset but the rest of the chip goes
through a normal system reset. The RST bit automatically clears during the system reset.
Following the system reset, the POR bit in the Reset Status and Control Register is set.
Fault Detect Logic Reset
Fault detect circuitry exists to detect illegal state changes which may be caused by tran-
sient power or electrostatic discharge events. When such a fault is detected, a system reset
is forced. Following the system reset, the FLTD bit in the Reset Status and Control Register
is set.
PS024604-1005
PRELIMINARY
External Pin Reset