Z8FMC16100 Datasheet, PDF (255/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
233
Watch-Dog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
Watch-Dog Timer is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±+/-50%. For operating frequencies below 2KHz, do not enable the
clock failure circuitry (POFEN must be deasserted in the OSCCTL register).
Clock Failure Detection and Recovery for WDT Oscillator
In the event of a Watch-Dog Timer oscillator failure, a System Exception will be issued if
the WDFEN bit of the OSCCTL register is set. This event does not trigger an attendant clock
switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no
longer possible to detect a primary oscillator failure.
The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look-
ing for a Watch-Dog Timer clock. The logic counts 8000 system clock cycles before deter-
mining that a failure occurred. The system clock rate determines the speed at which the
Watch-Dog Timer failure can be detected. A very slow system clock results in very slow
detection times. If the Watch-Dog Timer is the primary oscillator or if the Watch-Dog
Timer oscillator is disabled, deassert the WDFEN bit of the OSCCTL register.
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry, actively powers down the flash,
and selects the primary oscillator, which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two-step
sequence E7H followed by 18H to the Oscillator Control Register address unlocks it. The
register locks after completion of a register write to the OSCCTL.
Table 130. Oscillator Control Register (OSCCTL)
BITS
7
6
5
4
3
FIELD ^{INTEN XTLEN WDTEN POFEN WDFEN}
RESET
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
F86H
* The reset value is 1 if the option bit LPDEN is 0.
2
FLPEN
0*
R/W
1
0
SCKSEL
00
R/W
PS024604-1005
P R E L I M I N A R Y Clock Failure Detection and Recovery for WDT