Z8FMC16100 Datasheet, PDF (178/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
156
The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previ-
ous transaction suspended. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception is completed in both MASTER and SLAVE modes. A character can be
defined to be 1–8 bits by the NUMBITS field in the SPI Mode Register. In SLAVE mode, it
is not necessary for SS to deassert between characters to generate an interrupt. The SPI in
SLAVE mode can also generate an interrupt if the SS signal deasserts prior to transfer of
all the bits in a character (see description of slave abort error above). Writing a 1 to the
IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit
must be cleared to 0 by the interrupt service routine to generate future interrupts. To start
the transfer process, an SPI interrupt can be forced by software to write a 1 to the STR bit
in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the BIRQ bit in the SPICTL Register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT Register, just
the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI MASTER mode, the Baud Rate Generator creates a lower-frequency serial clock
(SCK) for data transmission synchronization between the master and the external slave.
The input to the Baud Rate Generator is from the system clock. The SPI Baud Rate High
and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI
Baud Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) =
2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value
of (2 x 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with an interrupt upon time-out. To configure the Baud Rate Generator as a timer with an
interrupt upon time-out, complete the following procedure:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and the associated interrupt by setting
the BIRQ bit in the SPI Control Register to 1.
Serial Peripheral Interface
PRELIMINARY
PS024604-1005