Z8FMC16100 Datasheet, PDF (193/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
171
S Start
W Write
A Acknowledge
A Not Acknowledge
P Stop
Master Write Transaction with a 7-Bit Address
Figure 28 illustrates the data transfer format from a master to a 7-bit addressed slave
S
Slave
W=0
A
Data
A
Data
A
Data
A/A P/S
Address
Figure 28. Data Transfer Format—Master Write Transaction with a 7-Bit Address
The procedure for a master transmit operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE mode with either a 7- or 10-bit slave address. The MODE field selects the
address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the IEN bit in the I²C Control Register.
2. The software asserts the TXI bit of the I²C Control Register to enable transmit inter-
rupts.
3. The I²C interrupt asserts, because the I²C Data Register is empty.
4. The software responds to the TDRE bit by writing a 7-bit slave address plus the Write
bit (which is cleared to 0) to the I²C Data Register.
5. The software sets the START bit of the I²C Control Register.
6. The I²C controller sends a START condition to the I²C slave.
7. The I²C controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of the address has been shifted out by the SDA signal, the transmit inter-
rupt asserts.
9. The software responds by writing the transmit data into the I²C Data Register.
10. The I²C controller shifts the remainder of the address and the Write bit out via the
SDA signal.
11. The I²C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
high period of SCL. The I²C controller sets the ACK bit in the I²C Status Register.
PS024604-1005
PRELIMINARY
Master Transactions