Z8FMC16100 Datasheet, PDF (175/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
153
Table 83. SPI Clock Phase and Clock Polarity Operation
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit
Edge
Falling
Rising
Rising
Falling
SCK Receive
Edge
Rising
Falling
Falling
Rising
SCK Idle
State
Low
High
Low
High
Transfer Format Phase Equals Zero
Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0.
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
1. The diagram can be interpreted as either a master or slave timing diagram because the
SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly con-
nected between the master and the slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MISO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Input Sample Time
SS
Figure 25. SPI Timing When Phase is 0
PS024604-1005
PRELIMINARY
SPI Clock Phase and Polarity Control