Z8FMC16100 Datasheet, PDF (228/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
206
Sample Settling Time Register
The Sample Settling Time Register, shown in Table 108, is used to program the length of
time from the SAMPLE/HOLD signal to the START signal, when the conversion can
begin. The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this reg-
ister to contain the number of clocks required to meet a 0.5 µs minimum settling time.
Table 108. Sample and Settling Time (ADCSST)
BITS
7
6
5
4
3
2
1
0
FIELD
Reserved
SST
RESET
0
1
1
1
1
1
R/W
R
R/W
ADDR
F74H
Bit
Position
[7:5]
Value
(H)
0H
Description
Reserved - Must be 0.
[4:0]
0H - FH Sample settling time in number of system clock periods to meet 0.5 µS minimum.
SST
Sample Time Register
The Sample Time Register, shown in Table 109, is used to program the length of active
time for the sample after a conversion has begun by setting the START bit in the ADC
Control Register or initiated by the PWM. The number of system clock cycles required for
sample time varies from system to system, depending on the clock period used. The sys-
tem designer should program this register to contain the number of system clocks required
to meet a 1 µs minimum sample time.
Analog-to-Digital Converter
PRELIMINARY
PS024604-1005