Z8FMC16100 Datasheet, PDF (177/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
155
Slave Operation
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, and WOR bits in the SPICTL Register and the NUM-
BITS field in the SPIMODE Register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL Register can be used, if appropriate, to force a start-
up interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Reg-
ister are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE
mode; therefore, the SPIBRH and SPIBRL registers do not require initialization.
If the slave contains data to send to the master, the data should be written to the SPIDAT
Register before the transaction starts (first edge of SCK when SS is asserted). If the SPI-
DAT Register is not written prior to the slave transaction, the MISO pin outputs the value
that is currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the
system clock frequency (X_IN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic that supports SPI communication protocols and rec-
ognizes when communication errors have occurred. The SPI Status Register indicates
when a data transmission error has been detected.
Overrun
An overrun error (write collision) indicates that a Write to the SPI Data Register was
attempted while a data transfer is in progress (in either MASTER or SLAVE modes). An
overrun sets the OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this
error flag. The SPI Data Register is not altered when a Write occurs while a data transfer is
in progress.
Mode Fault
A mode fault indicates when more than one master is trying to communicate at the same
time (a multimaster collision). The mode fault is detected when the enabled master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error flag.
Slave Mode Abort
In SLAVE mode, if the SS pin deasserts before all bits in a character have been trans-
ferred, the transaction aborts. When this condition occurs, the ABT bit is set in the
SPISTAT Register as well as the IRQ bit (which indicates that the transaction is complete).
PS024604-1005
PRELIMINARY
Slave Operation