Z8FMC16100 Datasheet, PDF (223/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
201
To avoid disrupting a conversion already in progress, the START bit can be read to indicate
ADC operation status (busy or available).
Caution: Starting a new conversion while another conversion is in progress will stop the conver-
sion in progress and the new conversion will not complete.
ADC Timing
Each ADC measurement consists of 3 phases:
1. Input sampling (programmable, minimum of 1.0µs)
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5µs)
3. Conversion is 13 ADCLK cycles.
Figure 37 illustrates the control and flow of an ADC conversion.
START bit
SAMPLE/HOLD
Internal signal
BUSY
Internal signal
Set by user
1.0 s sample period
Conversion period
Cleared by BUSY
Programmable
settling period
Figure 37. ADC Timing Diagram
13-clock
Conversion period
PS024604-1005
PRELIMINARY
ADC Timing