Z8FMC16100 Datasheet, PDF (102/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
80
PWM Control 1 Register
The PWM Control 1 (PWMCTL1) Register, shown in Table 49, controls portions of PWM
operation.
Table 49. PWM Control 1 Register (PWMCTL1)
BITS
FIELD
RESET
R/W
ADDR
7
6
RLFREQ[1:0]
00
R/W
5
INDEN
0
R/W
4
3
Pol45
Pol23
0
0
R/W
R/W
F21H
2
Pol10
0
R/W
1
0
PRES[1:0]
00
R/W
Bit
Position
Value
(H)
[7:6]
RLFREQ[1:0]
00
01
10
11
[5]
INDEN
0
1
[4]
1
Pol2
0
[3]
1
Pol1
0
[2]
1
Pol0
0
Description
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
Independent PWM Mode Enable
This bit may only be altered when PWEN (PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
PWM outputs operate as 6 independent channels.
Invert Ouput polarity for channel pair PWM2.
Non-inverted polarity for channel pair PWM2.
Invert Ouput polarity for channel pair PWM1.
Non-inverted polarity for channel pair PWM1.
Invert Ouput polarity for channel pair PWM0.
Non-inverted polarity for channel pair PWM0.
Pulse-Width Modulator
PRELIMINARY
PS024604-1005