Z8FMC16100 Datasheet, PDF (100/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
78
BITS
FIELD
RESET
R/W
ADDR
Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
7
6
5
4
3
2
1
0
DUTYL
00H
R/W
F31H, F33H, F35H, F37H, F39H, F3BH
Bit
Position
[7]
SIGN
Value
(H)
0
1
[6:0], [7:0]
DUTYH and
DUTYL
Description
Duty Cycle Sign
Duty Cycle is a positive two’s complement number.
Duty Cycle is a negative two’s complement number. Output is forced to the off-
state.
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
PWM Control 0 Register
The PWM Control 0 (PWMCTL0) Register, shown in Table 48, controls PWM operation.
Table 48. PWM Control 0 Register (PWMCTL0)
BITS
7
6
FIELD ^{PWMOFF OUTCTL}
RESET
0
0
R/W
R/W
R/W
ADDR
5
ALIGN
0
R/W
4
3
2
1
Reserved ADCTRIG Reserved READY
0
0
0
0
R/W
R/W
R/W
R/W
F20H
0
PWMEN
0
R/W
Pulse-Width Modulator
PRELIMINARY
PS024604-1005