Z8FMC16100 Datasheet, PDF (81/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
59
T0ENH—Timer 1 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
FIELD ^PWMENL
RESET
0
R/W
R/W
ADDR
6
FLTENL
0
R/W
5
4
3
ADCENL CMPENL T0ENL
0
0
0
R/W
R/W
R/W
FC2H
2
U0RENL
0
R/W
1
U0TENL
0
R/W
PWMENL—Pulse-Width Modulator Interrupt Request Enable Low Bit
FLTENL—Fault Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
CMPENL—Comparator Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
0
SPIENL
0
R/W
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority
encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by
setting bits in each register. Table 35 describes the priority control for IRQ1.
Table 35. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
x indicates the register bits from 0 through 7.
PS024604-1005
PRELIMINARY
IRQ1 Enable High and Low Bit Registers