Z8FMC16100 Datasheet, PDF (150/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
128
• Noise Filter Control (NFCTL[2:0]) input selects the width of the up/down saturating
counter digital filter. The available widths range from 4 bits to 11 bits.
• The digital filter output features hysteresis
• Provides an active low Saturated State output (FiltSatB) which is used as an indica-
tion of the presence of noise.
Architecture
Figure 17 illustrates how the noise filter is integrated with the LIN-UART for use on a
LIN network.
System
Clock
LIN-UART
RxD
FiltSatB
NFEN, NFCTL
TxD
Noise
Filter
RxD
RxD
GPIO
TxD
LIN
Transceiver
TxD
Figure 17. Noise Filter System Block Diagram
Operation
The figure below illustrates the operation of the noise filter both with and without noise.
The noise filter in this example is a 2-bit up/down counter which saturates at 00b and
11b. A 2-bit counter is shown for convenience, the operation of wider counters is similar.
The output of the filter switches from 1 to 0 when the counter counts down from 01b to
00b and switches from 0 to 1 when the counter counts up from 10b to 11b. The noise
filter delays the receive data by three System Clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (FiltSatB = 1 at center of bit time) does not mean the sam-
pled data is incorrect, just that the filter is not in its "saturated" state of all 1’s or all 0’s. If
FiltSatB = 1 when RxD is sampled during a receive character, the NE bit in the ModeSta-
tus[4:0] field is set. By observing this bit, an indication of the level of noise in the net-
work can be obtained.
LIN-UART
PRELIMINARY
PS024604-1005