Z8FMC16100 Datasheet, PDF (308/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
286
Table 164. Rotate and Shift Instructions (Continued)
Mnemonic
RLC
RR
RRC
SRA
SRL
SWAP
Operands
dst
dst
dst
dst
dst
dst
Instruction
Rotate Left through Carry
Rotate Right
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
eZ8 CPU Instruction Summary
Table 165 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 165. eZ8 CPU Instruction Summary
Assembly
Mnemonic
Address
Mode
Symbolic Operation dst src
ADC dst, src dst ← dst + src + C r r
r Ir
RR
R IR
R IM
IR IM
ADCX dst, src dst ← dst + src + C ER ER
ER IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
Op
Code(s)
(Hex)
12
13
14
15
16
17
18
19
Flags
Fetch Instr.
C Z S V D H Cycles Cycles
****0* 2
3
2
4
3
3
3
4
3
3
3
4
****0* 4
3
4
3
PS024604-1005
PRELIMINARY
eZ8 CPU Instruction Set