Z8FMC16100 Datasheet, PDF (206/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
184
12. The software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL
Register and by asserting the FLUSH bit of the I2CCTL Register.
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
STOP or RESTART condition on the bus.
14. The slave I²C controller asserts the STOP/RESTART interrupt (sets the SPRS bit in the
I2CISTAT Register).
15. The software responds to the STOP interrupt by reading the I2CISTAT Register and
clearing the SPRS bit.
I²C Data Register
The I²C Data Register, shown in Table 92, contains the data that is to be loaded into the
Shift Register to transmit onto the I²C bus. This register also contains data that is loaded
from the Shift Register after it is received from the I²C bus. The I²C Shift Register is not
accessible in the Register File address space, but is used only to buffer incoming and out-
going data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I²C controller is in SLAVE mode, and data is being received).
Table 92. I²C Data Register (I2CDATA)
BITS
7
6
5
4
3
2
1
0
FIELD
DATA
RESET
0
R/W
R/W
ADDR
F50H
I²C Interrupt Status Register
The read-only I²C Interrupt Status Register, shown in Table 93, indicates the cause of any
current I²C interrupt and provides status of the I²C controller. When an interrupt occurs,
one or more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The GCA and
RD bits do not generate an interrupt but rather provide status associated with the
SAM bit interrupt.
I2C Master/Slave Controller
PRELIMINARY
PS024604-1005