Z8FMC16100 Datasheet, PDF (211/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
189
BITS
FIELD
RESET
R/W
ADDR
Table 97. I²C State Register (I2CSTATE) - Description when DIAG = 0
7
6
5
ACKV
ACK
AS
0
0
0
R
R
R
4
3
DS
10B
0
0
R
R
F55H
2
RSTR
0
R
1
SCLOUT
X
R
0
BUSY
X
R
ACKV—ACK Valid
This bit is set if sending data (Master or Slave) and the ACK bit in this register is valid for
the byte just transmitted. This bit can be monitored if it is appropriate for software to ver-
ify the ACK value before writing the next byte to be sent. To operate in this mode, the data
register must not be written when TDRE asserts; instead, software waits for ACKV to assert.
This bit clears when transmission of the next byte begins or the transaction is ended by a
STOP or RESTART condition.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS—Address State
This bit is active High while the address is being transferred on the I²C bus.
DS—Data State
This bit is active high while the data is being transferred on the I²C bus.
10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a Master. After the START bit is set, if the five most-significant bits of the address are
11110B, this bit is set. When set, it is reset once the address has been sent.
RSTR—RESTART
This bit is updated each time a STOP or RESTART interrupt occurs (SPRS bit set in
I2CISTAT register).
0 = Stop condition
1 = Restart condition
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input register.
BUSY—I²C Bus Busy
0 = No activity on the I²C Bus.
1 = A transaction is underway on the I²C bus.
PS024604-1005
PRELIMINARY
I2C State Register