Z8FMC16100 Datasheet, PDF (194/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
172
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit, and clears the ACK bit in the I²C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXI bit. The I²C controller flushes the Transmit Data Register,
sends a STOP condition on the bus, and clears the STOP and NCKI bits. The transaction
is complete, and the following steps can be ignored.
12. The I²C controller loads the contents of the I²C Shift Register with the contents of the
I²C Data Register.
13. The I²C controller shifts the data out via the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the STOP bit of
the I²C Control Register (or the START bit to initiate a new transaction).
16. If no additional transaction is queued by the master, the software can clear the TXI bit
of the I²C Control Register.
17. The I²C controller completes transmission of the data on the SDA signal.
18. The I²C controller sends a STOP condition to the I²C bus.
Note:
If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I²C controller asserts the NCKI interrupt and halts. The software must ter-
minate the transaction by setting either the STOP bit (end transaction) or the START bit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSH bit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I²C controller hardware automatically flushes transmit data in this not
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 29 illustrates the data transfer format from a master to a 10-bit addressed slave.
S Slave Address W=0 A Slave Address A Data A Data
1st Byte
2nd Byte
A/A F/S
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XX bits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
I2C Master/Slave Controller
PRELIMINARY
PS024604-1005