Z8FMC16100 Datasheet, PDF (254/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
232
Table 129. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal Precision
Oscillator
• 5.5296 MHz
• This is the reset default.
• High precision possible when trimmed
• No external components required
External Crystal/
Resonator/
External Clock
Drive
• 0 to 20MHz
• Very high accuracy (dependent on
crystal/resonator or external source)
• Requires external components
• Configure Option Bits for correct
external oscillator mode
• Unlock and write Oscillator Control
Register (OSCCTL) to enable external
oscillator
• Wait for required stabilization time
• Unlock and write Oscillator Control
Register (OSCCTL) to select external
oscillator
Internal Watchdog
Timer Oscillator
• 10KHz nominal
• Low accuracy
• No external components required
• Low power consumption
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and select
Internal WDT oscillator
Unintentional accesses to the Oscillator Control Register (OSCCTL) can stop the chip by
switching to a nonfunctioning oscillator. Accidental alteration of the OSCCTL register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL register with the values E7H followed by 18H. A third write to the
OSCCTL register then changes the value of the register and returns the register to a locked
state. Any other sequence of oscillator control register writes has no effect. The values
written to unlock the register must be ordered correctly, but need not be consecutive. It is
possible to access other registers within the locking/unlocking operation.
Clock Selection Following System Reset
The Internal Precision Oscillator is selected following a System Reset. Startup code after
the System Reset may change the system clock source by unlocking and configuring the
OSCCTL register. If the LPDEN bit in Program Memory Address 0001H is zero, Flash
Low Power mode is enabled during reset. When Flash Low Power mode is enabled during
reset, the FLPEN bit in the Oscillator Control Register (OSCCTL) will be set and the DIV
field of the OSCDIV register will be set to 08h.
Clock Failure Detection and Recovery for Primary Oscillator
The Z8FMC16100 Series Flash MCU generates a System Exception when a failure of the
primary oscillator occurs if the POFEN bit is set in the OSCCTL Register. To maintain sys-
tem function in this situation, the clock failure recovery circuitry automatically forces the
Oscillator Control
PRELIMINARY
PS024604-1005