Z8FMC16100 Datasheet, PDF (144/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8 Encore!^® Motor Control Flash MCUs
Product Specification
122
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting LMST = 1, LSLV = 0, ABEN = 0, LinState[1:0]
= 11B. If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the
LinState[1:0] bits must be set = 00B by software.
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the TxBreakLength field of the LIN
Control Register. The transmission of the Break is performed by setting the SBRK bit in the
Control 0 Register. The LIN-UART starts the Break once the SBRK bit is set and any char-
acter transmission currently underway has completed. The SBRK bit is deasserted by hard-
ware once the break is completed.
The Synch character is transmitted by writing a 55H to the Transmit Data Register (TDRE
must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (TDRE must = 1 before writing).
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the TDRE bit asserts. If the trans-
mit data register is written after TDRE asserts, but before TXE asserts, the hardware inserts
one or two stop bits between each character as determined by the Stop bit in the Control0
register. Additional idle time occurs between characters if TXE asserts before the next
character is written.
If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (RDA bit will be set in the
Status0 register).
If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the REN bit in the Control0 register until the frame time
slot has completed.
LIN Sleep Mode
While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus may issue a Wake-
up message if it requires the master to initiate a LIN message frame. Following the Wake-
up message, the master wakes up and initiates a new message. A Wake-up message is
accomplished by pulling the bus low for at least 250 µs but less than 5 ms. Transmitting a
00h character is one way to transmit the wake-up message.
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up mes-
sage duration.
LIN-UART
PRELIMINARY
PS024604-1005