Z8FMC16100 Datasheet, PDF (275/402 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Flash MCUs

Z8FMC16100 Series Flash MCU
Product Specification
253
A reset and stop function can be achieved by writing 81H to this register. A reset and go
function is achieved by writing 41H to this register. If the device is in DEBUG mode, a run
function is implemented by writing 40h to this register.
A more detailed description of each bit follows the table.
Table 135. OCD Control Register (OCDCTL)
BITS
7
6
5
4
3
2
1
0
FIELD ^{DBGMODE BRKEN DBGACK BRKLOOP BRKPC BRKZRO Reserved}
RST
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
DBGMODE—Debug Mode
Setting this bit to 1 causes the device to enter Debug mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to resume
execution. This bit is automatically set when a BRK instruction is decoded and Break-
points are enabled.
0 = The device is running (operating in NORMAL mode).
1 = The device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
a Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. This bit
automatically clears itself when an acknowledge character is sent.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops
on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
PS024604-1005
PRELIMINARY
OCD Control Register