4524_M Datasheet, PDF (94/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
HARDWARE
CONTROL REGISTERS
Timer control register W4
W43
W42
W41
CNTR1 output control bit
PWM signal
“H” interval expansion function control bit
Timer 4 control bit
W40 Timer 4 count source selection bit
at reset : 00002
at power down : 00002
0 CNTR1 output invalid
1 CNTR1 output valid
0 PWM signal “H” interval expansion function invalid
1 PWM signal “H” interval expansion function valid
0 Stop (state retained)
1 Operating
0
XIN input
1 Prescaler output (ORCLK) divided by 2
R/W
TAW4/TW4A
W53
W52
Timer control register W5
Not used
Timer 5 control bit
W51
W50
Timer 5 count value selection bits
at reset : 00002
at power down : state retained
0
This bit has no function, but read/write is enabled.
1
0 Stop (state initialized)
1 Operating
W51 W50
Count value
0 0 Underflow occurs every 8192 counts
0 1 Underflow occurs every 16384 counts
1 0 Underflow occurs every 32768 counts
1 1 Underflow occurs every 65536 counts
R/W
TAW5/TW5A
Timer control register W6
at reset : 00002
at power down : state retained
W63 Timer LC control bit
W62
W61
W60
Timer LC count source selection bit
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
0 Stop (state retained)
1 Operating
0 Bit 4 (T54) of timer 5
1 Prescaler output (ORCLK)
0 CNTR1 output auto-control circuit not selected
1 CNTR1 output auto-control circuit selected
0 D7(I/O)/CNTR0 input
1 CNTR0 input/output/D7 (input)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
R/W
TAW6/TW6A
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-81