4524_M Datasheet, PDF (175/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.1 I/O pins
(13) Key-on wakeup control register K0
Table 2.1.13 shows the key-on wakeup control register K0.
Set the contents of this register through register A with the TK0A instruction.
The contents of register K0 is transferred to register A with the TAK0 instruction.
Table 2.1.13 Key-on wakeup control register K0
Key-on wakeup control register K0
at reset : 00002 at power down : state retained
Port P03
K03
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P02
K02
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P01
K01
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P00
K00
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
(14) Key-on wakeup control register K1
Table 2.1.14 shows the key-on wakeup control register K1.
Set the contents of this register through register A with the TK1A instruction.
The contents of register K1 is transferred to register A with the TAK1 instruction.
Table 2.1.14 Key-on wakeup control register K1
Key-on wakeup control register K1
at reset : 00002 at power down : state retained
Port P13
K13
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P12
K12
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P11
K11
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Port P10
K10
key-on wakeup control bit
0 Key-on wakeup not used
1 Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
R/W
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-11