4524_M Datasheet, PDF (198/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.3 Timers
2.3.2 Related registers
(1) Interrupt control register V1
Table 2.3.1 shows the interrupt control register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
at reset : 00002
at power down : 00002
R/W
V13 Timer 2 interrupt enable bit
0 Interrupt disabled (SNZT2 instruction is valid)
1 Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
V12 Timer 1 interrupt enable bit
0 Interrupt disabled (SNZT1 instruction is valid)
1 Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
V11 External 1 interrupt enable bit
0 Interrupt disabled (SNZ1 instruction is valid)
1 Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
V10 External 0 interrupt enable bit
0 Interrupt disabled (SNZ0 instruction is valid)
1 Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When timer is used, V11 and V10 are not used.
(2) Interrupt control register V2
Table 2.3.2 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.3.2 Interrupt control register V2
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
Timer 4, serial I/O interrupt 0 Interrupt disabled (SNZT4, SNZSI instruction is valid)
V23
enable bit
1 Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
V22 A/D interrupt enable bit
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZTAD instruction is invalid) (Note 3)
V21 Timer 5 interrupt enable bit
0 Interrupt disabled (SNZT5 instruction is valid)
1 Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
V20 Timer 3 interrupt enable bit
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When timer is used, V21 is not used.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-34