4524_M Datasheet, PDF (8/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
List of figures
List of figures
CHAPTER 1 HARDWARE
Pin configuration (top view) (4524 Group) .................................................................................... 3
Block diagram (4524 Group) ........................................................................................................... 4
Port block diagram (1) .................................................................................................................... 10
Port block diagram (2) .................................................................................................................... 11
Port block diagram (3) .................................................................................................................... 12
Port block diagram (4) .................................................................................................................... 13
Port block diagram (5) .................................................................................................................... 14
Port block diagram (6) .................................................................................................................... 15
Port block diagram (7) .................................................................................................................... 16
Port block diagram (8) .................................................................................................................... 17
Fig. 1 AMC instruction execution example .................................................................................. 18
Fig. 2 RAR instruction execution example .................................................................................. 18
Fig. 3 Registers A, B and register E ........................................................................................... 18
Fig. 4 TABP p instruction execution example ............................................................................. 18
Fig. 5 Stack registers (SKs) structure .......................................................................................... 19
Fig. 6 Example of operation at subroutine call .......................................................................... 19
Fig. 7 Program counter (PC) structure ........................................................................................ 20
Fig. 8 Data pointer (DP) structure ................................................................................................ 20
Fig. 9 SD instruction execution example ..................................................................................... 20
Fig. 10 ROM map of M34524ED .................................................................................................. 21
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure ............................................................ 21
Fig. 12 RAM map ............................................................................................................................ 22
Fig. 13 Program example of interrupt processing ...................................................................... 24
Fig. 14 Internal state when interrupt occurs ............................................................................... 24
Fig. 15 Interrupt system diagram .................................................................................................. 24
Fig. 16 Interrupt sequence ............................................................................................................. 26
Fig. 17 External interrupt circuit structure ................................................................................... 27
Fig. 18 External 0 interrupt program example-1 ......................................................................... 30
Fig. 19 External 0 interrupt program example-2 ......................................................................... 30
Fig. 20 External 0 interrupt program example-3 ......................................................................... 30
Fig. 21 External 1 interrupt program example-1 ......................................................................... 31
Fig. 22 External 1 interrupt program example-2 ......................................................................... 31
Fig. 23 External 1 interrupt program example-3 ......................................................................... 31
Fig. 24 Auto-reload function .......................................................................................................... 32
Fig. 25 Timer structure (1) ............................................................................................................ 34
Fig. 26 Timer structure (2) ............................................................................................................ 35
Fig. 27 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”) ...................................... 42
Fig. 28 CNTR1 output auto-control function by timer 3 ............................................................ 43
Fig. 29 Timer 4 count start/stop timing ....................................................................................... 44
Fig. 30 Watchdog timer function ................................................................................................... 45
Fig. 31 Program example to start/stop watchdog timer ............................................................ 46
Fig. 32 Program example to enter the mode when using the watchdog timer ..................... 46
Fig. 33 A/D conversion circuit structure ...................................................................................... 47
Fig. 34 A/D conversion timing chart ............................................................................................. 50
Fig. 35 Setting registers ................................................................................................................. 50
Fig. 36 Comparator operation timing chart .................................................................................. 51
Fig. 37 Definition of A/D conversion accuracy ........................................................................... 52
Rev.2.00 Aug, 06 2004
iv
REJ09B0107-0200Z