4524_M Datasheet, PDF (220/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.5 Serial I/O
2.5 Serial I/O
The 4524 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data.
This section describes serial I/O functions, related registers, application examples using serial I/O and
notes.
2.5.1 Carrier functions
Serial I/O consists of the serial I/O register SI, serial I/O control register J1, serial I/O transmit/receive
completion flag SIOF and serial I/O counter.
A clock-synchronous serial I/O uses the shift clock generated by the clock control circuit as a synchronous
clock. Accordingly, the data transmit and receive operations are synchronized with this shift clock.
In transmit operation, data is transmitted bit by bit from the SOUT pin synchronously with the falling edges
of the shift clock.
In receive operation, data is received bit by bit from the SIN pin synchronously with the rising edges of the
shift clock.
Note: 4524 Group only supports LSB-first transmit and receive.
s Shift clock
When using the internal clock of 4524 Group as a synchronous clock, eight shift clock pulses are
output from the SCK pin when a transfer operation is started. Also, when using some external clock
as a synchronous clock, the clock that is input from the SCK pin is used as the shift clock.
s Data transfer rate (baudrate)
When using the internal clock, the data transfer rate can be determined by selecting the instruction
clock divided by 2, 4 or 8.
When using an external clock, the clock frequency input to the SCK pin determines the data transfer
rate.
Figure 2.5.1 shows the serial I/O block diagram.
1/8
1/4
INSTCK
1/2
D6/SCK ^SCK
D5/SOUT ^SOUT
J13J12
00
01
10
11
Synchronous
circuit
Serial I/O counter (3)
QS
R
SIN
D4/SIN
MSB Serial I/O register (8) LSB
J11 J10
TABSI
TSIAB
TABSI
Register B (4) Register A (4)
Fig. 2.5.1 Serial I/O block diagram
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
SIOF
Serial I/O
interrupt
SST
instruction
Internal reset signal
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