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4524_M Datasheet, PDF (200/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES
4524 Group
APPLICATION
2.3 Timers
(6) Timer control register W2
Table 2.3.6 shows the timer control register W2.
Set the contents of this register through register A with the TW2A instruction.
In addition, the TAW2 instruction can be used to transfer the contents of register W2 to register A.
Table 2.3.6 Timer control register W2
Timer control register W2
at reset : 00002 at power down : state retained
W23 CNTR0 output selection bit
0 Timer 1 underflow signal divided by 2 output
1 Timer 2 underflow signal divided by 2 output
W22 Timer 2 control bit
0 Stop (state retained)
1 Operating
W21 W20
Count source
W21 Timer 2 count source selection 0 0 System clock (STCK)
bits
0 1 Prescaler output (ORCLK)
W20
1 0 Timer 1 underflow signal (T1UDF)
1 1 PWM signal (PWMOUT)
Note: “R” represents read enabled, and “W” represents write enabled.
R/W
(7) Timer control register W3
Table 2.3.7 shows the timer control register W3.
Set the contents of this register through register A with the TW3A instruction.
In addition, the TAW3 instruction can be used to transfer the contents of register W3 to register A.
Table 2.3.7 Timer control register W3
Timer control register W3
at reset : 00002 at power down : state retained R/W
W33
W32
W31
W30
Timer 3 count auto-stop circuit 0 Timer 3 count auto-stop circuit not selected
control bit (Note 2)
1 Timer 3 count auto-stop circuit selected
Timer 3 control bit
0 Stop (state retained)
1 Operating
W31 W30
Count source
Timer 3 count source selection 0 0 PWM signal (PWMOUT)
bits (Note 3)
0 1 Prescaler output (ORCLK)
1 0 Timer 2 underflow signal (T2UDF)
1 1 CNTR1 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
3: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-36