4524_M Datasheet, PDF (188/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
➀ Disable Interrupts
External 0 interrupt is temporarily disabled.
Interrupt enable flag INTE 0
Interrupt control register V1
b3
b0
✕✕✕ 0
↓
➁ Set Port
Port used for external 0 interrupt is set to input port.
Register Y
b3
b0
1000
Port D8 output latch 1
➂ Set Valid Waveform
Valid waveform of INT0 pin is selected.
Interrupt control register I1
↓
b3
b0
1✕1✕
➃ Execute NOP Instruction
↓
[NOP]
↓
➄ Clear Interrupt Request
External 0 interrupt activated condition is cleared.
All interrupts disabled [DI]
b0: External 0 interrupt occurrence disabled [TV1A]
Specify bit position of port D [TYA]
Set to input [SD]
[TI1A]
b3: INT0 pin input enabled
b1: Both edges detection selected
External 0 interrupt request flag EXF0 0
External 0 interrupt activated condition cleared [SNZ0]
↓
( ) Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction
according to the interrupt request flag EXF0,
insert the NOP instruction after the SNZ0 instruction.
↓
➅ Enable Interrupts
The External 0 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
✕ ✕ ✕ 1 b0: External 0 interrupt occurrence enabled [TV1A]
Interrupt enable flag INTE 1
All interrupts enabled [EI]
↓
External 0 interrupt enabled state
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.2 External 0 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-24