4524_M Datasheet, PDF (191/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V1
0
b3
b0
✕0 ✕✕
All interrupts disabled [DI]
b2: Timer 1 interrupt occurrence disabled [TV1A]
➁ Stop Timer Operation
Timer 1 is temporarily stopped.
Timer 1 count source is selected.
Timer control register W1
↓
b3
b0
0000
[TW1A]
b3: Timer 1 count auto-stop circuit not selected
b2: Timer 1 stop
b1, b0: Instruction clock (INSTCK) selected for
Timer 1 count source
↓
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown *A below.)
Timer 1 reload register R1 “A616”
Timer count value 166 set [T1AB]
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F 0
↓
Timer 1 interrupt activated condition cleared
[SNZT1]
↓
( ) Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction
according to the interrupt request flag T1F,
insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer Operation
Timer 1 temporarily stopped is restarted.
Timer control register W1
↓
b3
b0
0100
b2: Timer 1 operation start [TW1A]
↓
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
✕ 1 ✕ ✕ b2: Timer 1 interrupt occurrence enabled [TV1A]
Interrupt enable flag INTE 1
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The timer 1 count value to make the interrupt occur every 0.25 ms is set as follows.
0.25 ms ≅ (2.0 MHz)^-1 ✕ 3 ✕ (166+1)
System clock Instruction Timer 1 count value
clock
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.5 Timer 1 constant period interrupt setting example
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-27