4524_M Datasheet, PDF (292/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
APPENDIX
3.3 List of precautions
3.3 List of precautions
3.3.1 Program counter
Make sure that the PCH does not specify after the last page of the built-in ROM.
3.3.2 Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels.
However, one of stack registers is used respectively when using an interrupt service routine and when
executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
3.3.3 Notes on I/O port
(1) Note when ports P0, P1, P4 and D0–D7 are used as an input port
In the following conditions, the pin state of port P0, P1, P4 or D0–D7 is transferred as input data to
register A when the corresponding input instruction is executed.
• Set bit i (i=0, 1, 2 or 3) of register FR0, FR1, FR2 or FR3 to “0” according to the port to be used.
• Set the output latch of the specified port to “1” with the corresponding output instruction.
If bit i of FR0, FR1, FR2 or FR3 is “0” and the output latch is set to “0,” “0” is output to specified
port.
If bit i of FR0, FR1, FR2 or FR3 is “1”, the output latch value is output to specified port.
(2) Note when ports P2 and P3 are used as an input port
In the following condition, the pin state of port P2 or P3 is transferred as input data to register A when
the IAP2 or IAP3 instruction is executed.
• Set the output latch of specified port P2i or P3i (i=0, 1, 2 or 3) to “1” with the OP2A or OP3A
instruction.
If the output latch is “0”, “0” is output to specified port P2 or P3.
(3) Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the VDD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM
version.
Connect the CNVSS/VPP pin to VSS through an approximate 5 kΩ resistor which is connected to the
CNVSS/VPP pin at the shortest distance.
(4) Multifunction
• Be careful that the output of ports D8 and D9 can be used even when INT0 and INT1 pins are selected.
• Be careful that the input of ports D4–D6 can be used even when SIN, SOUT and SCK pins are selected.
• Be careful that the input/output of port D7 can be used even when input of CNTR0 pin is selected.
• Be careful that the input of port D7 can be used even when output of CNTR0 pin is selected.
• Be careful that the “H” output of port C can be used even when output of CNTR1 pin is selected.
(5) Connection of unused pins
Table 3.3.1 shows the connections of unused pins.
(6) SD, RD, SZD instructions
When the SD and RD instructions are used, do not set “10102” or more to register Y.
When the SZD instructions is used, do not set “10002” or more to register Y.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-38