4524_M Datasheet, PDF (23/310 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES

4524 Group
HARDWARE
PORT BLOCK DIAGRAM
PORT BLOCK DIAGRAMS
Clock (input) for timer 3 event count
PWMOD
SCP instruction
RCP instruction
Register Y
W31
W30
SQ
(Note 1)
C/CNTR1 (Note 2,
Note 3)
R
Decoder
D
QRT
Timer 3 underflow signal
W32
W61
Skip decision
(SZD instruction)
SD instruction
RD instruction
CLD
instruction
Register Y
Decoder
FR10
S
RQ
Skip decision
(SZD instruction)
(Note 1)
D0 (Note 2)
SD instruction
RD instruction
CLD
instruction
Register Y
Decoder
FR11
S
RQ
Skip decision
(SZD instruction)
(Note 1)
D1 (Note 2)
SD instruction
RD instruction
CLD
instruction
Register Y
Decoder
FR12
S
RQ
Skip decision
(SZD instruction)
(Note 1)
D2 (Note 2)
SD instruction
RD instruction
CLD
instruction
FR13
S
RQ
(Note 1)
D3 (Note 2)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: When CNTR1 input is selected, output transistor is turned OFF.
Port block diagram (1)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-10